Static Timing Analysis for Nanometer Designs: A Practical Approach
Big Sale Best Cheap Deals Static Timing Analysis for Nanometer Designs: A Practical Approach
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Big Sale Best Cheap Deals Static Timing Analysis for Nanometer Designs: A Practical Approach
The book covers topics such as cell timing and power modeling; interconnect modeling and ysis, delay calculation, crosstalk, noise and the chip timing verification using static timing ysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.
The static timing ysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.
This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for ysis of internal paths as well as IO interfaces. Advanced modeling and ysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces also covered.
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